Conventional dynamic memory devices such as dynamic random access memory (DRAM) require that all rows be refreshed once each refresh interval (typically 64 ms) to preserve the data that is stored in the RAM. If the data is not refreshed, then over time, the charge that encodes the data in the memory cells leaks away. In fact, most DRAM rows can go many seconds between refresh operations at the high temperature limit and can retain data even longer at typical temperatures. Typically, the short refresh interval results from a few ‘leaky’ memory cells. Only the ‘leaky’ memory cells actually need the fast refresh rate. Unnecessarily refreshing all rows at the rate required by the ‘leaky’ memory cells wastes considerable power when the DRAM is not otherwise being used (i.e., in a standby mode). Wasting power is particularly objectionable in mobile applications that store power in batteries.
Thus, there is a need for reducing refresh rates and/or other issues associated with the prior art.